In semiconductor technologies, multiple chips can be bonded to a semiconductor wafer, referred to as chip-to-wafer bonding, to achieve three dimensional packing with high packing density, short wiring, and improved reliability and quality. The chip-to-wafer bonding technology has various applications including imaging sensors, memory devices, micro-electro-mechanical systems, to name a few. When semiconductor technologies increase integrated circuit (IC) pattern density and shrink feature size of the IC pattern, there are high requirements on bonding environment and bonding efficiency. However, the current chip-to-wafer bonding tools experience issues including oxygen contamination associated with contact degradation and low throughput associated with high fabrication cost which hinder the process.